Just got this board a few days ago! Thank yous go to mahen, who was kind enough to sponsor the board for me (thanks again man, I really appreciate it!). For those not familiar with it, this board is the basis of MiSTer, which is a project that aims to recreate various classic computers, game consoles, and arcade machines on FPGA hardware – and as the name implies, you could say it is a continuation of the MiST…
I know there wasn’t much updates on the minimig status, but with good (;)) reason: I’ve been pretty busy, so I had little time to work on minimig updates. I did spend quite some time on rewriting the CPU <-> minimig interface, which will hopefully reduce timing problems and enable me to finally add the ethernet Zorro interface. The CPU clock will also be reduced to 28MHz, hopefully that won’t affect the CPU speed much. This is quite…
QMEM bus specification This post describes the QMEM bus, the different cycles allowed, the bus elements and different bus configurations supported. 1. Introduction 2. Features 3. Signals Description 4. Cycles Description 5. Bus Elements 6. Bus Configurations Introduction QMEM (abbreviated from quick memory), is a flexible, portable, simple and fast system interconnect bus, specifically targeted at SoC systems for their inter-chip communication needs. QMEM is based on synchronous memory bus with added flow control signals,…
The OR1200 is a RISC-type, Harvard architecture (separate instruction and data buses) synthesizable CPU core, written by the OpenCores community. It can be configured with a number of optional components, such as cache, MMU, FPU, timer, programmable interrupt controller, debug unit, etc. For sake of simplicity, I decided to disable most of the optional components, except the hardware multiplier and divider, all other features will be added if/when needed. The OR1200 has standard GNU tools available,…
