Skip to content

Tag: FPGA

qSoC – The OR1200 CPUCPU (from: https://www.flickr.com/photos/2top/10402551773/)

qSoC – The OR1200 CPU

Published by chaos on June 28, 2016

The OR1200 is a RISC-type, Harvard architecture (separate instruction and data buses) synthesizable CPU core, written by the OpenCores community. It can be configured with a number of optional components, such as cache, MMU, FPU, timer, programmable interrupt controller, debug unit, etc. For sake of simplicity, I decided to disable most of the optional components, except the hardware multiplier and divider, all other features will be added if/when needed. The OR1200 has standard GNU tools available,…

Continue readingqSoC – The OR1200 CPU
qSoC, or how to build an FPGA SoC from scratchSoC

qSoC, or how to build an FPGA SoC from scratch

Published by chaos on April 29, 2016

Introduction I’d like to talk about how to build a fast, lean, clean SoC machine. What is an SoC? An SoC, or a System On a Chip, is, simply put, a microprocessor with some common peripherals attached, like ROM, RAM, SDRAM controller, UART, SPI, GPIO, and other I/O ports or protocols, all tied up into a system. An SoC is not unlike a microcontroller, which also has a microprocessor bundled with some sort of memory…

Continue readingqSoC, or how to build an FPGA SoC from scratch

minimig AGA v1.2 for the MiST board released

Published by chaos on February 21, 2016

There is a new release of minimig-AGA for the MiST board available, grab it on the minimig-mist page! While the CPU is still not as stable as I’d like, the latest bitfield fixes by Till Harbaum fixed a lot of games and demos that didn’t work properly before. The OSD Turbo option is not needed or recommended for games or demos anymore, but could still be used for a little speed up in Workbench or programs. F11…

Continue readingminimig AGA v1.2 for the MiST board released

Upgrading minimig with AGA capabilities, Part 2

Published by chaos on November 30, 2014

So, to continue from Part 1, the rest of additions in Denise. Denise bitplane updates First, of  course, the bitplane count needs to be upgraded from ECS’ 6 bitplanes to AGA’s 8 bitplanes, together with everything dependent on it, like collision detection for 8 bitplanes, two additional bitplane output buffer registers, playfield support, etc. Quite a lot of code changes in this step, but not hard to do – basically, I just followed the existing code and…

Continue readingUpgrading minimig with AGA capabilities, Part 2