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Month: June 2016

qSoC – The QMEM bus

QMEM bus specification This post describes the QMEM bus, the different cycles allowed, the bus elements and different bus configurations supported. 1. Introduction 2. Features 3. Signals Description 4. Cycles Description 5. Bus Elements 6. Bus Configurations Introduction QMEM (abbreviated from quick memory), is a flexible, portable, simple and fast system interconnect bus, specifically targeted at SoC systems for their inter-chip communication needs. QMEM is based on synchronous memory bus with added flow control signals,…

qSoC – The OR1200 CPU

The OR1200 is a RISC-type, Harvard architecture (separate instruction and data buses) synthesizable CPU core, written by the OpenCores community. It can be configured with a number of optional components, such as cache, MMU, FPU, timer, programmable interrupt controller, debug unit, etc. For sake of simplicity, I decided to disable most of the optional components, except the hardware multiplier and divider, all other features will be added if/when needed. The OR1200 has standard GNU tools available,…