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qSoC – The OR1200 CPUCPU (from: https://www.flickr.com/photos/2top/10402551773/)

qSoC – The OR1200 CPU

Published by chaos on June 28, 2016

The OR1200 is a RISC-type, Harvard architecture (separate instruction and data buses) synthesizable CPU core, written by the OpenCores community. It can be configured with a number of optional components, such as cache, MMU, FPU, timer, programmable interrupt controller, debug unit, etc. For sake of simplicity, I decided to disable most of the optional components, except the hardware multiplier and divider, all other features will be added if/when needed. The OR1200 has standard GNU tools available,…

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qSoC, or how to build an FPGA SoC from scratchSoC

qSoC, or how to build an FPGA SoC from scratch

Published by chaos on April 29, 2016

Introduction I’d like to talk about how to build a fast, lean, clean SoC machine. What is an SoC? An SoC, or a System On a Chip, is, simply put, a microprocessor with some common peripherals attached, like ROM, RAM, SDRAM controller, UART, SPI, GPIO, and other I/O ports or protocols, all tied up into a system. An SoC is not unlike a microcontroller, which also has a microprocessor bundled with some sort of memory…

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HRTmon & Updating NMI vector

Published by chaos on November 2, 2014

One of the features added on the 68010+ Motorola CPUs is a special register called VBR – Vector Base Register, which allows the OS or user program to move the CPU’s vector table away from 68000‘s fixed address $00000 to some other address. On the Amiga, this was usually used to move the vector table to fastRAM, enabling somewhat faster interrupt processing. One of the utilities that allowed this was VBRMove. I usually have VBRMove…

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